The present invention relates to a semiconductor device, and more particularly to a semiconductor device with a reduced layout area having a shared metal line between pads.
The fast-paced advancement of semiconductor technologies is evidenced in rapidly increasing memory capacity processing speed.
In general, pads are placed in a peripheral region of a semiconductor chip to allow electrical connection between the chip and the outside. These pads are used to input or output the signals to/from the chip such as the signals related to address, command input, read and write operations, etc. Each of these pads connected to the internal circuit of the chip is connected to the package pin via a wire bonding.
Each of these pads is provided with a vicinity circuit region adjacent thereto. Each vicinity circuit region is the area set aside to accommodate the circuits connect directly to the pad, for example, an electrostatic discharge unit, a data output driver circuit, an on-die termination (ODT) circuit, and the like. Each pad's use or purpose is determined by the connection made of the pad and the circuit provided in the vicinity circuit area, and further the pad is packaged in the manner suitable for the packaging required by a user.
FIG. 1A shows an electrostatic discharge unit formed at a periphery region of a pad, and FIG. 1B shows a layout of the electrostatic discharge unit shown in FIG. 1A.
Referring to FIG. 1A, an electrostatic discharge unit 20 disposed between a pad 10 and an internal circuit 40, and a power clamp unit 30 disposed between a power voltage VDD line 1 and a ground voltage VSS line 2 are comprised in a semiconductor device.
In the electrostatic discharge unit 20, a diode 21 connected to the power voltage VDD line 1 and a diode 22 connected to the ground voltage VSS line 2 are connected in series. When static electricity is inputted into the pad, the static electricity is discharged through the power voltage VDD line 1 or the ground voltage VSS line 2. The power clamp unit 30 is formed between the power voltage VDD line 1 and the ground voltage VSS line 2 and is turned on to protect the device when the voltage is rapidly changed by an electrostatic input.
FIG. 1B is a layout of the electrostatic discharge unit of FIG. 1A. However, FIG. 1B is not shown with the details of the electrostatic discharge unit 20 and the power clamp 30, because they are deemed to be apparent to one of ordinary skills in the pertinent art. Instead, FIG. 1B is drawn to show with emphasis the metal lines and contacts related to power supply.
Referring to FIG. 1B, the electrostatic discharge units 21, 22, 23, 24 and power clamp units 31, 32, 33, 34 are disposed at the upper portion and lower portion of the pads 10 and 11. The metal lines 41, 42, 43, 44 are disposed to apply bias to the power clamp units 31, 32, 33, 34.
The diodes 21, 22 of the electrostatic discharge unit 20 are formed to be overlapped with the pad 10 and are connected to the power voltage VDD line 1 or the ground voltage VSS line 2 through a contact. Specifically, one side of the first diode 21 is connected to the power voltage VDD line 1, and the other side of the first diode 21 is connected to the ground voltage VSS line 2. In other words, an N-type impurity region of the first diode 21 is connected to the VDD line 1 at the lower portion thereof through the contact, and a P-type impurity region of the first diode 21 is connected to the pad 10 through a metal option (not shown). Therefore, the first diode 21 can protect the circuit by discharging static electricity applied to the pad to the power voltage VDD line 1. Likewise, a P-type impurity region of the second diode 22 is connected to the ground voltage VSS line 2 through the contact, and an N-type impurity region of the second diode 22 is connected to the pad 10 through a metal option (not shown).
Next, with respect to the power clamp unit 30, the power clamp unit 30 in FIG. 1A corresponds to power clamp units 31, 32 in FIG. 1B. The first power clamp unit 31 is formed with a contact at a portion thereof overlapped with the power voltage VDD line 1 and is supplied with the power voltage VDD. Also, the first power clamp unit 31 is connected to the ground voltage VSS line 2 through the metal line 41. Likewise, the second power clamp unit 32 is formed with a contact at a portion thereof overlapped with the ground voltage VSS line 2 to be supplied with the ground voltage VSS, and the second power clamp unit 32 is supplied with the power voltage VDD through the metal line 42.
A drain terminal of the first power clamp unit 31 is supplied with the power voltage VDD through the contact formed at the portion overlapped with the power voltage VDD line 1 and a source terminal of the first power clamp unit 31 is supplied with the ground voltage VSS through the metal line 41. Also, a drain terminal of the second power clamp unit 32 is supplied with the power voltage VDD through metal line 42, and a source terminal of the second power clamp unit 32 is supplied with the ground voltage VSS through the contact formed at the portion overlapped with the ground voltage VSS line 2.
Further, the electrostatic discharge units 23, 24 and the power clamp units 33, 34 are disposed at a periphery of the pad 11, and the metal lines 43, 44 are formed so as to apply bias to the power clamp units 33, 34.
Generally, wiring of more than 6 μm width is used for the metal lines 41, 42, 43, 44. However, since signal lines are more and more increasing as semiconductor devices are more miniaturized and operate at higher speed, it is very difficult to ensure a space for disposing the metal lines for the power supply.
Uniticularly, according to the prior art, since two power lines exist within a pitch between the pads, it is very difficult to allocate a space for disposing the signal line.